1. Field of the Invention
The present invention generally relates to using lateral field capacitor structures to increase the capacitance density per unit area in integrated circuit capacitors, and in particular to using novel lateral-field optimal high efficient capacitor structures that maximize the flux usage in the interlayer metal separation region, as well as, in the metal layer region.
2. Description of Related Art
Capacitors are essential elements in integrated circuits, such as sample and holds, analog-to-digital (A/D) and digital-to-analog (D/A) converters, switched-capacitor and continuous-time filters, as well as, radio frequency (RF) blocks. In many of these applications, capacitors consume a large portion of a chip""s area. Thus, the capacitor""s area efficiency is of primary importance. In analog applications, the other desired properties for capacitors are close matching of adjacent capacitors, linearity, small bottom-plate capacitor, and to a lesser degree, the absolute accuracy of the value (i.e., tolerance). In RF applications, it is essential for the capacitors to have self-resonance frequencies, well in excess of the frequency of interest and large quality factors (Q). Good linearity and large breakdown voltage are the other two desired properties for a good RF capacitor.
Several approaches have been taken to improve the area efficiency of capacitors. For example, nonlinear capacitors with high capacitance density, such as junction or gate oxide capacitors have been used for a long time in applications where the linearity and the quality factor, Q, of the capacitors are not important. Unfortunately, these capacitors need a dc bias and are strongly process and temperature dependent. In high precision circuits, such as data converters, their use is limited to bypass and coupling capacitors, or varactors in RF circuits.
On the other hand, metal-to-metal and metal-to-poly capacitors have very good linearity and quality factors, Q. However, they suffer from a low capacitance density. The low capacitance density manly arises from large metal-to-metal/metal-to-poly vertical spacing that determines the capacitance in the horizontal parallel plate (HPP) structure 100, shown in FIG. 1. Unfortunately, in today""s process technologies, this large vertical spacing does not shrink as fast as the lateral separation to avoid excessive crosstalk between the digital metal lines in different layers. Thus, the parallel plate capacitors consume a larger fractional die area. Although an extra processing step involving depositing a thin layer of insulator between two metal or poly layers can mitigate the vertical spacing problem to some extent, this extra step is not available in many of the standard silicon-based technologies. Even if such special capacitor layers were available, the parallel plate structure does not necessarily result in the highest possible capacitance density
The capacitance density can be improved by structures that exploit both lateral and vertical electric field components. A well known example of such structures is the interdigitated parallel wire structure 200 (also know as Horizontal Bars or HB), as shown in FIG. 2. Recently, several new structures were suggested as methods of obtaining higher capacitance per unit area. These structures include: a quasi-fractal structure 208; a woven structure 202 connected using vias 210 (the top view 204 of the woven structure 202 is also shown); and a second woven structure 206 without via 210 interconnections. The new structures 200, 202, 206, and 208 essentially demonstrate the same linearity as the HPP structure 100 (shown in FIG. 1), including both the metal-to-metal/poly capacitors. The only difference between the new structures 200, 202, 206, and 208 and the HPP structure 100 (shown in FIG. 1) is the higher capacitance densities. These structures 200, 202, 206, and 208 also provide lower bottom-plate capacitance, since more field lines end up on the adjacent metal line, as opposed to the substrate
Despite these advantages, quasi-fractal structures 208 and woven structures 202 and 206 have not been widely used in the signal path of analog circuits because predicting their absolute capacitor value can be complicated and time consuming. Also, it is not clear that the quasi-fractal structures 208 and woven structures 202 and 206 are always advantageous over the more regular structures, such as the interdigitated parallel wire structures 200.
Thus, there is a need in the art for new capacitor structures with high efficiency, which demonstrate higher capacitance density and superior matching properties, as compared to the standard HPP structures 100 (shown in FIG. 1) and previously reported quasi fractal structures 208 (shown in FIG. 2) and woven structures 202 and 206 (shown in FIG. 2).
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the specification discloses several capacitor structures that demonstrate high capacitance density, superior matching, tolerances, and self-resonance frequencies.
The first embodiment of the present invention is referred to herein as a vertical parallel plate (VPP) structure. In accordance with the first embodiment, a capacitor structure comprises a plurality of vertical plates. The vertical plates are substantially parallel to each other, and each vertical plate comprises multiple conducting strips. These conducting strips are substantially parallel to each other and are connected to each other by one or more vias. The vertical plates are alternately connected to each other, creating a first portion of the vertical plates and a second portion of the vertical plates, such that the first portion of the vertical plates forms a first terminal of the capacitor structure, and the second portion of the vertical plates forms a second terminal of the capacitor structure. Either slotted vias, interleaving vias or individual vias can be used to connect the conducting strips.
The second embodiment of the present invention is referred to herein as a vertical bars (VB) structure. In accordance with the second embodiment of the present invention, a capacitor structure comprises a plurality of rows of vertical bars, wherein within each row, the vertical bars are parallel to each other, and each vertical bar comprises multiple conducting patches. These conducting patches are connected to each other by one or more vias. The rows of vertical bars form a first direction and a second direction, wherein the second direction is orthogonal to the first direction. In the first direction, the vertical bars are alternately connected to each other, creating a first portion of the vertical plates and a second portion of the vertical plates. The first portion of the vertical plates forms a section of the first terminal of the capacitor structure, and the second portion of the vertical plates forms a section of the second terminal of the capacitor structure. In the second direction, the vertical bars are alternately connected to each other, creating a third portion of the vertical plates and a fourth portion of the vertical plates. The third portion of the vertical plates forms a remaining section of the first terminal of the capacitor structure, and the fourth portion of the vertical plates forms a remaining section of the second terminal of the capacitor structure.
Each patch has a lateral size. The lateral size affects the effective series resistance of the capacitor structure. The lateral size also affects the quality factor of the capacitor structure.
The fourth embodiment is similar to the first embodiment, and it is referred to herein as a two-layer VPP. The two-layer VPP structure comprises two VPP structures, wherein the first VPP is positioned in a first direction. The second VPP is located on top of the first VPP, and the second VPP is positioned in a second direction The second direction is orthogonal to the first direction.
The fifth embodiment is also similar to the first embodiment, and it is referred to herein as a multiple-layer VPP. The multiple-layer VPP structure comprises multiple (more than two) VPP structures, wherein a previous VPP is positioned in a first direction. A subsequent VPP is located on top of the previous VPP, and the subsequent VPP is positioned in a second direction. The second direction is orthogonal to the first direction.
Each of the above-described embodiments have utility for providing a capacitor structure with high efficiency, which results in higher capacitance density and superior matching and tolerance properties, as compared to prior art capacitor structures.